Figure 19
A byte transmission can be seen as a rotate operation between the value stored in an 8-bit shift register in the
master device (host microcontroller) and the value stored in an 8-bit shift register in the transceiver. The SCK line
is used to synchronize both SPI bit transfers. Data is transferred full-duplex from master to slave through the SDI
line and from slave to master through the SDO line. The most significant bit is always sent first. In both directions
the rising SCK edge is used to sample a bit, and the falling SCK edge shifts the bits through the shift register.
The nSS_CONFIG or nSS_DATA signals are asserted by the master device and should remain low during a byte
transmission. The transmission is synchronized by these nSS_CONFIG or nSS_DATA signals. While the
nSS_CONFIG or nSS_DATA is set to 1, the counters controlling transmission are reset. Reception starts with the
first clock cycle after the falling edge of nSS_CONFIG or nSS_DATA. If either signal goes high during a byte
transmission the counters are reset and the byte must be retransmitted.
The configuration interface is selected if nSS_CONFIG is low even if the TRC105 is in buffered mode and
nSS_DATA is low (nSS_CONFIG has priority). To configure the transceiver two bytes are required. The first byte
contains a 0 start bit, R/W information (1 = read, 0 = write), 5 bits for the address of the register and a 0 stop bit.
The second byte contains the data to be sent in write mode or the new address to read from in read mode.
Figure 20
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TRC105 - 05/29/13
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